Design of a novel congestion-aware communication mechanism for wireless NoC architecture in multicore systems

Hybrid Wireless Network-on-Chip (WNoC) architecture is emerged as a scalable communication structure to mitigate the deficits of traditional NOC architecture for the future Multi-core systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing cores. Sharing links between cores increases congestion vulnerability which consequently degrades WNoC performance. In this paper, we propose a novel congestion-aware mesh-based WNoC architecture to address these issues. We consider optimization of the system cost and performance, simultaneously. Through comprehensive simulations, the performance of the proposed architecture has been evaluated and compared with notable WNoC architectures. The experimental results demonstrated the effectiveness of the proposed design under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption.